`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/02 20:03:00
// Design Name: 
// Module Name: led_breathe
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module led_breathe(
    input               sys_clk_i               ,
    input               sys_rst_n_i             ,

    output              led_o                   
);
reg[20:0] ccr;
reg[20:0] cnt;

assign led_o = ( cnt < ccr) ? 1'b1 : 1'b0;

always @( posedge sys_clk_i or negedge sys_rst_n_i ) begin
    if( sys_rst_n_i == 1'b0 )
        cnt <= 'd0;
    else if( cnt == 'd200000 )
        cnt <= 'd0;
    else
        cnt <= cnt + 1'b1;
end

always@( posedge sys_clk_i or negedge sys_rst_n_i ) begin
    if( sys_rst_n_i == 1'b0 )
        ccr <= 'd0;
    else if( cnt == 'd200000 )
        if( ccr == 'd180000 )
            ccr <= 'd200;
        else
            ccr <= ccr + 'd200;
    else
        ccr <= ccr;
end



endmodule
